Whereas the majority of consideration on TSMC is geared toward its modern nodes, reminiscent of N3E and N2, a great deal of chips will proceed to be made utilizing extra mature and confirmed course of applied sciences for years to come back. Which is why TSMC has continued to refine its present nodes, together with its current-generation 5nm-class choices. To that finish, at its North American Expertise Symposium 2024, the corporate launched a brand new, optimized 5nm-class node: N4C.
TSMC’s N4C course of belongs to the corporate’s 5nm-class household of fab nodes and is a superset of N4P, essentially the most superior know-how in that household. In a bid to additional deliver down 5nm manufacturing prices, for TSMC is implementing a number of modifications for N4C, together with rearchitecting their commonplace cell and SRAM cell, altering some design guidelines, and lowering the variety of masking layers. Because of these enhancements, the corporate expects N4C to attain each smaller die sizes in addition to a discount in manufacturing complexity, which in flip will deliver die prices down by as much as 8.5%. Moreover, with the identical wafer-level defect density fee as N4P, N4C stands to supply even increased practical yields because of its die space discount.
“So, we aren’t carried out with our 5nm and 4nm [technologies],” stated Kevin Zhang, Vice President of Enterprise Growth at TSMC. “From N5 to N4, we now have achieved 4% density enchancment optical shrink, and we proceed to boost the transistor efficiency. Now we herald N4C to our 4 nm know-how portfolio. N4C permits our prospects to scale back their prices by take away among the masks and to additionally enhance on the unique IP design like a typical cell and SRAM to additional scale back the general product degree value of possession.”
TSMC says that N4C can use the identical design infrastructure as N4P, although it’s unclear whether or not N5 and N4P IP could be re-used for N4C-based chips. In the meantime, TSMC signifies that it provides varied choices for chipmakers to search out the correct steadiness between value advantages and design effort, so corporations concerned with adopting a 4nm-class course of applied sciences might nicely undertake N4C.
The event of N4C comes as lots of TSMC’s chip design prospects are getting ready to launch chips based mostly on the corporate’s ultimate era of FinFET course of know-how, the 3nm N3 sequence. Whereas N3 is predicted to be a profitable household, the excessive prices of N3B have been a difficulty, and the era is marked by diminishing efficiency and transistor density returns altogether. Consequently, N4C might nicely turn into a serious, long-lived node at TSMC, serving as a very good match for patrons who need to keep on with a less expensive FinFET node.
“It is a very vital enhancement, we’re working with our buyer, principally to extract extra worth from their 4 nm funding,” Zhang stated.
TSMC expects to start out quantity manufacturing of N4C chips a while subsequent yr. And with TSMC having produced 5nm-class for practically half a decade at that time, N4C ought to have the ability to hit the bottom operating when it comes to quantity and yields.